1. Field
The present invention relates generally to a clock doubler including duty cycle correction. More specifically, the present invention relates to embodiments for generating a clock signal based on a corrected duty cycle.
2. Background
Clock signals, which may be generated with various types of oscillator and supporting circuitry, are commonly used in many electronics circuits and for various purposes. For example, clock signals may be used to trigger synchronous circuits (e.g., flip-flops) in digital circuits such as processors, memory devices, and so on.
A clock signal, which has a duty cycle that is determined by the time duration at logic high and the time duration at logic low, continually transitions between logic high and logic low. It may be desirable to generate a clock signal having a duty cycle that is as close to 50% as possible, so that the logic high time duration is close to the logic low time duration. A digital circuit may use both the rising and falling edges of the clock signal to trigger synchronous circuits to achieve faster operating speed. A 50% duty cycle for the clock signal may then provide the synchronous circuits with maximum timing margins.
A duty cycle of a clock signal may be distorted due to various phenomena such as mismatches in transistor devices used to generate the clock signal. Great care is often used in designing clock generation and distribution circuits to minimize device mismatches. Digital circuits fabricated with advanced IC processes typically operate at high speed, e.g., one giga-Hertz (GHz) or higher. The high speed corresponds to a smaller clock period, e.g., 1 nanosecond (nsec) for 1 GHz. Small circuit mismatches may then translate to a relatively large error in duty cycle with the smaller clock period.
The clock duty cycle problem is often addressed by running an oscillator at twice the desired frequency and dividing an oscillator output signal by two to generate a clock signal with a good duty cycle. However, this approach may be undesirable or inadequate for several reasons. First, more power is consumed to operate the oscillator and the divide-by-2 circuit at twice the desired frequency. Second, significant duty cycle distortion may still be present in the clock signal due to random device mismatches in the divide-by-2 circuit.
A need exists for a clock doubler. More specifically, a need exists for embodiments related to a clock doubler for generating a clock signal based on a corrected a duty cycle.